Isolation structure configurations for modifying stresses in semiconductor devices

ABSTRACT

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to apparatus and methods for modifying stresses in semiconductor devices. In particular, the present invention relates to modifying isolation structure configurations, such as trench depth and isolation materials used, to either induce or reduce tensile and/or compressive stresses on an active area of MOS semiconductor devices.

2. State of the Art

Semiconductor integrated circuits are formed by chemically and physically forming circuit components in and on a semiconductor substrate. These circuit components are generally conductive (e.g., for conductor and resistor fabrication) and may be of different conductivity types (e.g., for transistor and diode fabrication). Thus, when forming such circuit components, it is essential that they are electrically isolated from one another, wherein electrical communication between the isolated circuit components is achieved through discrete electrical traces.

Various techniques have been developed for electrically isolating integrated circuit components formed in the semiconductor substrate. One such technique is known as trench isolation. The trench isolation technique involves forming a channel or trench in the semiconductor substrate, usually by etching techniques well known in the art. The trench is formed to surround the circuit components to be isolated and filled with a dielectric material, thereby electrically isolating the circuit components.

FIGS. 22 and 23 illustrate in side cross-sectional view and in top plan view, respectively, components of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). As shown in FIG. 22, a source region 202 and a drain region 204 are implanted in a semiconductor substrate 206. The source region 202 and the drain region 204 may be implanted with either a p-type material, such as boron, to form a pMOS (p-channel Metal Oxide Semiconductor) transistor or an n-type material, usually phosphorous and/or arsenic, to form an nMOS (n-channel Metal Oxide Semiconductor) transistor.

A gate structure 208 spans a region of the semiconductor substrate 206 between the source region 202 and the drain region 204. An exemplary gate structure 208 comprises a conductive material 212 electrically isolated with dielectric spacers 214 and 214′ adjacent the source region 202 and the drain region 204, a lower dielectric layer 216, and a cap layer 218.

The source region 202 and the drain region 204 are isolated with an isolation structure 222 (i.e., a dielectric-filled trench) extending into the semiconductor substrate 206, preferably beyond the depth of the source region 202 and the drain region 204, as shown in FIG. 22. The isolation structure 222 surrounds the source region 202 and the drain region 204, as shown in FIG. 23, to form an island or active area 224. The material which form the gate structure 208 extends beyond the active area 224 to other semiconductor device components (not shown).

It has been reported in literature that stresses on an active area can significantly effect the performance of MOS devices. Hamada in “A New Aspect of Mechanical Stress Effects in Scaled MOS Device”, IEEE Transactions on Electron Devices, vol. 38 (1991), pp. 895-900 illustrated that stresses of the order of 100 MPa can affect performance by a few percent. In the reported experiments, well-controlled uniaxial stresses were applied on MOS devices by using a 4-point bending technique. The stresses were applied both parallel and perpendicular to the channel current direction and for both NMOS and pMOS devices. The results showed that for nMOS devices, tensile stress in both directions improves performance, while compressive stress degrades performance. These effects have been found to be more significant for long channel nMOS devices. For pMOS devices, tensile stress perpendicular to the channel current direction improves performance, but tensile stress parallel to the channel current direction degrades performance, and vice versa for compressive stress.

Such degradation in performance is particularly a problem for MOS devices in flip-chip packaging configurations. FIG. 24 illustrates a cross-sectional view of such a packaging configuration. With flip-chip packaging configurations, a semiconductor die 232 is electrically attached to a carrier substrate 234, such as a printed circuit board, with the active surface 236 of the semiconductor die 232 facing the carrier substrate 234. The electrical attachment of the semiconductor die active surface 236 to the carrier substrate 234 is generally achieved by refluxing solder balls 238 between the semiconductor die active surface 236 and the carrier substrate 234 to form an electrical connection between electrical traces on or in the semiconductor die 232 (not shown) and electrical traces on the carrier substrate 234 (not shown). Once electrical attachment of the semiconductor die 232 to the carrier substrate 234 is complete, an underfill material 242 is disposed between the semiconductor die 232 and the carrier substrate 234. The resulting structure is then heated to cure the underfill material 242. However, when the resulting structure is cooled down to room temperature from the underfill cure temperature, a bending curvature develops because the carrier substrate 234 contracts more than the semiconductor die 232 (i.e., due to the thermal expansion mismatch between the carrier substrate 234 and the semiconductor die 232), as shown in FIG. 25. Such bending causes biaxial compressive stresses (illustrated by arrows 248 in FIG. 25) on MOS transistors 246 (shown schematically as rectangles in FIGS. 24 and 25) within the semiconductor die 232.

As previously discussed, these biaxial stresses will degrade nMOS device performance. However, these biaxial stresses will have less of an effect on the performance of a pMOS device due to the cancellation effects of the two perpendicular stress components (i.e., the decrease in performance due to compressive stress perpendicular to the channel current direction is offset by the increase in performance due to the compressive stress parallel to the channel current direction).

Therefore, it would be advantageous to develop a technique to effectively induce or reduce tensile and/or compressive stresses on the active area of a MOS device to improve the operating performance thereof, while utilizing commercially-available, widely-practiced semiconductor device fabrication techniques.

SUMMARY OF THE INVENTION

The present invention relates to apparatus and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device. In specific, the present invention relates to a semiconductor device having an active area formed in a semiconductor substrate and an isolation structure comprising at least one dielectric material disposed within a trench which extends into said semiconductor substrate, wherein the isolation structure substantially surrounds the active area, and wherein at least a portion of the isolation structure is adapted to modify stresses incurred on the active area.

The modification of isolation structure configurations is an effective technique of controlling stresses on a semiconductor device active because the isolation structure is on the same relative plane as the active area and, of course, any device structures formed therein. This shared plane allows for a direct transfer or abatement of stresses incurred on the active area due to packaging or other external stress sources.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings to which:

FIGS. 1 and 2 are side cross-sectional and top plan views, respectively, of an nMOS device having stress modifying isolation structures for accommodating compressive stress, according to the present invention;

FIG. 3 is a side cross-sectional view of the NMOS device of FIGS. 1 and 2 under compressive stress, according to the present invention;

FIG. 4 is a stress model of the effect of the effect of compressive stress applied to a semiconductor die;

FIGS. 5 and 6 are side cross-sectional and top plan views, respectively, of a pMOS device having stress modifying isolation structures for optimizing pMOS performance when under compressive stress, according to the present invention;

FIG. 7 is a cross-sectional view of a back-bonded packaging configuration;

FIG. 8 is a cross-sectional view of the back-bonded packaging configuration of FIG. 7 under stress due to the thermal expansion mismatch;

FIG. 9 is a top plan view of a pMOS device having stress modifying isolation structures for optimizing pMOS performance when under tensile stress, according to the present invention;

FIG. 10 is a side cross-sectional view of a pMOS device having stress modifying isolation structures when under tensile stress, according to the present invention;

FIGS. 11 and 12 are side cross-sectional and top plan view, respectively, of an nMOS device having tensile stress-inducing, dielectric material disposed in an isolation structure, according to the present invention;

FIG. 13 is a top plan view of a pMOS device having tensile stress-inducing and compressive stress-inducing, dielectric material disposed in an isolation structure, according to the present invention;

FIGS. 14 and 15 is a model structure and a graph of the results of a numerical simulation using the finite element method for the model structure, respectively, according to the present invention;

FIGS. 16 and 17 are side cross-sectional and top plan views, respectively, of an nMOS device having deep isolation structures for accommodating compressive stress, according to the present invention;

FIG. 18 is a side cross-sectional view of a pMOS device having deep isolation structures, according to the present invention;

FIG. 19 is a top plan view of a pMOS device having stress modifying isolation structures for optimizing pMOS performance when under compressive stress, according to the present invention;

FIG. 20 is a top plan view of a pMOS device having stress modifying isolation structures for optimizing pMOS performance when under tensile stress, according to the present invention;

FIG. 21 is a side cross-sectional view of an isolation structure having a conformal barrier layer, according to the present invention;

FIGS. 22 and 23 are side cross-sectional and top plan views, respectively, of components of a MOSFET, as known in the art;

FIG. 24 is a side cross-sectional view of a flip-chip packaging configuration, as known in the art; and

FIG. 25 is a side cross-sectional view of the flip-chip package configuration of FIG. 24 bending under thermal expansion mismatch stresses, as known in the art.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

Although FIGS. 1-21 illustrate various views of the present invention, these figures are not meant to portray semiconductor devices in precise detail. Rather, these figures illustrate semiconductor devices in a manner to more clearly convey the concepts of the present invention. Additionally, elements common between the figures retain that same numeric designation.

It is recognized that it would be advantageous to modify the stresses acting upon the active area of a MOS device in order to improve performance. Such stress modification might be achieved at the packaging level by applying stresses to the semiconductor die. However, semiconductor dice are usually brittle and break easily under stress. Additionally, it is very difficult to apply a uniform stress across an entire semiconductor die. Thus, an attempt to apply a uniform stress across the semiconductor die would likely result in a non-uniform stress which would, in turn, result in undesirable performance variations in the MOS devices across the semiconductor die.

FIGS. 1 and 2 illustrate an embodiment of the present invention for an nMOS device 100. The nMOS device 100 comprises an n-type source region 102 and an n-type drain region 104, which are implanted into a semiconductor substrate 106, such as a silicon wafer, by any known implantation technique. A gate structure 108 spans a region of the semiconductor substrate 106 between the source region 102 and the drain region 104. Generally, the gate structure 108 comprises a conductive material 112 electrically isolated with dielectric spacers 114 and 114′ adjacent the source region 102 and the drain region 104, respectively, a lower dielectric layer 116, and a cap layer 118.

The source region 102 and the drain region 104 are isolated with an isolation structure 122, which extends into the semiconductor substrate 106. The isolation structure 122 surrounds the source region 102 and the drain region 104, as shown in FIG. 2, to form an active area 124. The isolation structure 122 includes a dielectric material 126, which has a lower modulus than the semiconductor substrate 106 (i.e., more compliant than the semiconductor substrate 106). Exemplary low-modulus, dielectric materials 126 include, but are not limited to, polymers and porous oxides. As shown in FIG. 3, when compressive stresses (shown as arrows 128 in FIGS. 2 and 3) are incurred on the semiconductor die, such as through flip-chip packaging stress, the low-modulus, dielectric material 126 deforms, thereby eliminating or lessening the detrimental effect of the compressive stress 128 on the active area 124. FIG. 4 shows a stress model, which illustrates this effect using the finite element method. FIG. 4 shows that under 100 MPa compressive stress applied to a semiconductor die front surface, the average stress in the active area (the vertical axis) depends on the modulus of the trench dielectric material. The horizontal axis is the active area dimension along the direction of applied stress. Curve A represents a trench filled with a silicon dioxide with a modulus of between about 70 and 80 GPa, as commonly used as a dielectric material in the industry. Curve B represents a similar trench filled with a complaint dielectric material, specifically polyimide with a modulus of about 5 GPa. Thus, FIG. 4 illustrates that compressive stress on the active areas can be reduced by using more compliant dielectric materials. This compressive stress reduction is more significant for smaller dimension active areas.

FIGS. 5 and 6 illustrate another embodiment of the present invention for a pMOS device 130. The pMOS device 130 is similar in structure to the nMOS device 100 illustrated in FIGS. 1 and 2 with the exception that the pMOS device 130 has a p-type source region 132 and a p-type drain region 134, as shown in FIG. 5. As previously discussed for pMOS devices, tensile stress perpendicular to the channel current direction improves performance, but tensile stress parallel to the channel current direction degrades performance, and vice versa for compressive stress. As shown in FIG. 6, to improve the performance of the pMOS device, the low-modulus, dielectric material 126 is placed in the isolation structure 122 parallel to the channel current direction to eliminate or lessen the detrimental compressive stress perpendicular to the channel current direction. Furthermore, a high-modulus (stiff), dielectric material 136 is placed in the isolation structure 122 perpendicular to the channel current direction to translate the beneficial compressive stress parallel (shown as arrows 128) to the channel current direction to the active area 124. The high-modulus, dielectric material 136 should have a modulus equal to or higher than a modulus of the semiconductor substrate 106. Therefore, any stresses incurred on the high-modulus, dielectric material 136 will also be incurred on active area 124 with substantially the same force (shown as arrows 138). Exemplary high-modulus, dielectric materials 136 include, but are not limited to, silicon nitride and silicon dioxide, which are deposited to have compressive stresses.

It is, of course, understood that the use of low-modulus, dielectric material can also improve pMOS device performance in back-bonded packaging configurations. FIGS. 7 and 8 illustrate a back-bonded package 140. With back-bonded packaging configurations, a back surface 142 of a semiconductor die 144 is attached to a carrier substrate 146. Electrical communication between the semiconductor die 144 and the carrier substrate 146 is generally achieved by bond wires 148 extending between electrical traces (not shown) on or in an active surface of the semiconductor die 144 and electrical traces (not shown) on the carrier substrate 146. The attachment of the semiconductor die back surface 142 to the carrier substrate 146 achieved with an adhesive material 152, such as an epoxy resin, as shown in FIG. 7. The resulting structure is then heated to cure the adhesive material 152. However, when the resulting structure is cooled down to room temperature from the adhesive material cure temperature, a bending curvature develops because the carrier substrate 146 contracts more than the semiconductor die 144 (i.e., due to the thermal expansion mismatch between the carrier substrate 146 and the semiconductor die 144), as shown in FIG. 7. Such bending causes biaxial tensile stresses (illustrated by arrows 154 in FIG. 8) on the MOS transistors (shown schematically as rectangles 156 in FIG. 8) within the semiconductor die 144.

Of course, these biaxial tensile stresses enhance the performance of NMOS devices, but have little effect on the performance of a pMOS device, due to the cancellation effects of the two perpendicular stress components. However, the low-modulus, dielectric material 126 can be used to improve the performance a pMOS device. As shown in FIG. 9, the low-modulus, dielectric material 126 is placed in the isolation structure 122 perpendicular to the channel current direction to eliminate or lessen the detrimental tensile stress parallel to the channel current direction of pMOS device 150. The parallel tensile stress is eliminated or lessened, because when parallel tensile stress (shown as arrows 154 in FIG. 9) is incurred on the semiconductor die, the low-modulus, dielectric material 126 stretches, as shown in FIG. 10, thereby eliminating or lessening the detrimental effect of the tensile stress 128 on the active area 124. Furthermore, referring to FIG. 9, a high-modulus (stiff), dielectric material 136 may be placed in the isolation structure 122 parallel to the channel current direction to translate the beneficial tensile stress perpendicular to the channel current direction to the active area 124 (translated tensile stress shown as arrows 158).

FIGS. 11 and 12 illustrate yet another embodiment of the present invention for an NMOS device 160. The nMOS device 160 illustrated in FIGS. 11 and 12 is similar in structure to the NMOS device 100 illustrated in FIGS. 1 and 2. However, with the present embodiment, the isolation structure 122 includes a dielectric material 162, which has tensile stress-inducing properties (e.g., it creates a tensile stress on adjacent structures and/or materials). Exemplary tensile stress-inducing, dielectric materials 162 include, but are not limited to, silicon nitride which has been deposited to have large tensile stresses. As shown in FIG. 11, the tensile stress-inducing, dielectric material 162 creates a tensile stress (shown as arrows 164) on the active area 124 thereby improving the performance of the NMOS device, even when no external stresses are incurred on the semiconductor die. However, when compressive stresses (shown as arrow 128 in FIG. 12) are incurred on the semiconductor die, the tensile stress-inducing, dielectric material 162 creates the tensile stress (shown as arrows 164) on the active area 124 in a direction opposite the compressive stresses 128, which eliminates or lessens the detrimental effect of the compressive stress 128.

FIG. 13 illustrates a still another embodiment of the present invention for a pMOS device 170. The pMOS device 170 is similar in structure to the pMOS device 130 illustrated in FIGS. 5 and 6. As previously discussed for pMOS devices, tensile stress perpendicular to the channel current direction improves performance, but tensile stress parallel to the channel current direction degrades performance, and vice versa for compressive stress. Thus, to improve the performance of the pMOS device, the tensile stress-inducing, dielectric material 162 is placed in the isolation structure 122 parallel to the channel current direction to eliminate or lessen the detrimental compressive stress perpendicular to the channel current direction. Furthermore, a compressive stress-inducing, dielectric material 166 may be placed in the isolation structure 122 perpendicular to the channel current direction to induce the beneficial compressive stress (shown as arrows 168) parallel to the channel current direction to the active area 124. The compressive stress-inducing, dielectric material 166 creates a compressive stress on adjacent structures and/or materials. Exemplary compressive stress-inducing, dielectric materials 166 include, but are not limited to, silicon nitride and silicon dioxide which are deposited to have compressive stresses. Thus, the configuration shown in FIG. 13 improves the performance of the pMOS device when no external stresses are incurred on the semiconductor die or when biaxial compressive or tensile stresses are incurred on the semiconductor die.

A further embodiment of the present invention involves increasing isolation structure depth to reduce compressive stresses. FIGS. 14 and 15 illustrate a model structure and a graph of the results of a numerical simulation using the finite element method for the model structure, respectively. In FIG. 14, A is the active area width (or length), B is the isolation structure width, H is the trench depth and D is the active area depth. In the simulation, the trench width B was fixed at 0.5 microns (stress incurred on the active area is not significantly sensitive to trench width) and the active region depth D is fixed at 0.25 um (i.e., a typical active region depth). Thus, the active area width A and isolation structure depth H are variables. FIG. 15 illustrates the simulation results with a dielectric material having a modulus of about 5 GPa, wherein the horizontal axis is the trench depth H, and the vertical axis is the compressive stress in the active area normalized by the semiconductor die/packaging thermal mismatch stress (i.e., applied stress). The simulation was performed for three active area widths (i.e., A=2.0 um corresponding to curve A1, A=1.0 um corresponding to curve A2, and A=0.5 um corresponding to curve A3) covering a range of interest. As FIG. 15 illustrates for all the three active area widths, the compressive stresses decreased and approached zero with an increase of trench depth. Furthermore, it is observed that the smaller the active area width A, the less the active area is affected by the applied stress. The increased trench depth makes the carrier substrate 106 more flexible. Thus, when a dielectric material which is more compliant than the carrier substrate is used, the stress on the active area is decreased. Preferably, the structure should have a trench depth H to active area width A aspect ratio (i.e., H/A) of greater than about 0.5.

FIGS. 16 and 17 illustrates the deep trench embodiment of the present invention for an nMOS device 172. The nMOS device 172 illustrated in FIG. 16 is similar in structure to the NMOS device 100 illustrated in FIG. 1. However, with the present embodiment, the isolation structure depth is increased to form deep isolation structure 174. The increased depth of the deep isolation structure 174 has been found to reduce compressive stresses on the active area 124. FIG. 17 illustrates a configuration wherein the deep isolation structure 174 surrounds the active area 124. The deep isolation structure 174 includes a dielectric material 178 disposed therein. With the deep isolation structure 174, a standard dielectric material 178, such as silicon dioxide, may be used to isolate the active area 124. However, to further enhance the reduction in compressive stress, the dielectric material 178 may be a low-modulus dielectric material (such as described in regard to FIGS. 1 and 2) or a tensile stress-inducing, dielectric material (such as described in regard to FIGS. 11 and 12).

FIG. 18 illustrates the deep trench embodiment of the present invention for a pMOS device 180 with the deep trenches formed perpendicular to the channel current direction. The pMOS device 180 illustrated in FIG. 18 is similar in structure to the nMOS device 130 illustrated in FIG. 5.

As illustrated in FIG. 19, when the pMOS device 180 is subjected to biaxial compressive stresses (e.g., flip-chip packaging configurations), the isolation structure depth is increased only in portions 182 of the isolation structure 122 which are parallel to the channel current direction in order to eliminate or lessen the detrimental compressive stresses perpendicular to the channel current direction. In order to further reduce detrimental compressive stresses on the active area 124 perpendicular to the channel current direction, a low-modulus dielectric material (such as described in regard to FIG. 6) or a tensile stress-inducing, dielectric material (such as described in regard to FIG. 13) may be disposed in isolation structure portions 182. Portions 184 of the isolation structure 122 which are perpendicular to the channel current direction are of a depth sufficient to isolate the active area 124, but may translate beneficial compressive stress to the active area 124 parallel to the channel current direction. In order to further translate or induce beneficial compressive stress to the active area 124 parallel to the channel current direction, the isolation structure portions 184, a high-modulus dielectric material (such as described in regard to FIG. 6) or a compressive stress-inducing, dielectric material (such as described in regard to FIG. 13) may be disposed in isolation structure portions 184.

When the pMOS device 190 is subjected to biaxial tensile stresses (e.g., back-bonded packaging configurations), the isolation structure depth is increased for the isolation structure depth is increased only in portions 192 of the isolation structure 122 which are perpendicular to the channel current direction in order to eliminate or lessen the detrimental tensile stresses parallel to the channel current direction, as shown in FIG. 20. In order to further reduce detrimental tensile stresses on the active area 124 perpendicular to the channel current direction, a low-modulus dielectric material (such as described in regard to FIG. 6) or a compressive stress-inducing, dielectric material (such as described in regard to FIG. 13) may be disposed in isolation structure portions 192. Portions 194 of the isolation structure 122 which are parallel to the channel current direction are of a depth sufficient to isolate the active area 124, but may translate beneficial tensile stress to the active area 124 perpendicular to the channel current direction. In order to further translate or induce beneficial tensile stress to the active area 124 perpendicular to the channel current direction, the isolation structure portions 194, a high-modulus dielectric material (such as described in regard to FIG. 9) or a tensile stress-inducing, dielectric material (such as described in regard to FIG. 13) may be disposed in isolation structure portions 194.

It is also understood, that the introduction of various low-modulus and high-modulus dielectric material, and compressive stress-inducing and tensile stress-inducing, dielectric materials may degrade the interface between the active area and the dielectric material and cause leakage problems. Thus, a thin conformal barrier layer 196, such as a conformal layer of silicon dioxide 196 may be deposited in the isolation structure 122 prior to depositing any of the various dielectric materials 198, as shown FIG. 21.

Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof. 

1-30. (canceled)
 31. A structure comprising: a substrate; a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of strain, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material; and a first trench structure disposed in a trench wherein the trench is proximate at least one side of one of the first source region and the first drain region, the first trench structure inducing only a portion of the first type of strain in the first channel region.
 32. The structure of claim 31, further comprising: a strained layer disposed over the substrate, wherein at least a portion of the first channel region is disposed in the strained layer, and the strained layer comprises at least one of a group II, group III, group V, and group VI element.
 33. The structure of claim 31, further comprising: a first strain-inducing element that induces strain in the first channel region; and a second strain-inducing element that induces strain in the first channel region, wherein the portion of the strain induced by the first trench structure is approximately zero and the first strain-inducing element is different from the second strain-inducing element.
 34. The structure of claim 33 wherein the first strain-inducing element comprises a first cap layer disposed over a surface of the first transistor.
 35. The structure of claim 33 wherein the first strain-inducing element comprises the first gate.
 36. The structure of claim 33 wherein the first strain-inducing element comprises at least one of the first source region and the first drain region.
 37. A method for forming a semiconductor structure, the method comprising: providing a substrate; forming a first transistor over a first region of the substrate by: defining a first source region and a first drain region in a first portion of the substrate, defining a first channel region between the first source region and the first drain region, the first channel region having a first type of strain, and forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material; and forming a first trench proximate at least one side of one of the first source region and the first drain region; and forming a first trench structure in the first trench, the first trench structure tailored to induce only a portion of the first type of strain in the first channel region.
 38. The method of claim 37 wherein at least a portion of the strain in the first channel region is induced by the first gate.
 39. The method of claim 37, further comprising: providing a first strain-inducing element; and providing a second strain-inducing element different from the first strain-inducing element, wherein the portion of the strain induced by the first trench structure is approximately zero.
 40. The method of claim 39 wherein the first strain-inducing element comprises a first cap layer disposed over a surface of the first transistor.
 41. The method of claim 39 wherein the first strain-inducing element comprises the first gate.
 42. The method of claim 39 wherein the first strain-inducing element comprises at least one of the first source region and the first drain region.
 43. The structure of claim 31, further comprising: a dielectric layer disposed beneath the first channel region.
 44. The structure of claim 31 wherein at least one of the first source region and the first drain region comprises a metal-semiconductor alloy, and the strain in the first channel region is induced by the metal-semiconductor alloy.
 45. The structure of claim 31 wherein the first transistor is disposed in a chip, the structure further comprising: a package housing the chip, wherein the package induces strain in the first channel region.
 46. The structure of claim 33 wherein the first strain-inducing element comprises a metal-semiconductor alloy region disposed within at least one of the first source region and the first drain region.
 47. The method of claim 37, further comprising: forming a metal-semiconductor alloy over at least one of the first source region and the first drain region, the metal-semiconductor alloy tailored to induce the first type of strain in the first channel region.
 48. The method of claim 38 wherein forming the first gate comprises depositing an overlayer over the first gate and annealing the first gate.
 49. The method of claim 38 wherein forming the first gate comprises forming a polycrystalline semiconductor layer over the substrate and reacting the polycrystalline semiconductor layer with a metal such that the first gate consists essentially of an alloy of the metal and the semiconductor layer.
 50. The method of claim 37 wherein the first transistor is disposed in a chip, the method further comprising: attaching the chip to a package, wherein at least a portion of the strain in the first channel region is induced by the package.
 51. The method of claim 39 wherein the first strain-inducing element comprises a metal-semiconductor alloy formed over at least one of the first source region and the first drain region.
 52. A method for forming a semiconductor structure, the method comprising: providing a substrate comprising a strained layer having a first type of strain; forming a masking layer over the substrate such that the masking layer exerts a second type of strain on the strained layer; removing the masking layer over a first portion of the substrate; and etching a trench in the first portion of the substrate.
 53. The method of claim 52 wherein the first type of strain and the second type of strain are different.
 54. The method of claim 52 wherein the masking layer comprises silicon nitride.
 55. The method of claim 52, further comprising forming a pad oxide layer over the substrate prior to forming the masking layer.
 56. A structure comprising: a substrate; a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of stress, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material; and a first isolation structure disposed in a trench wherein the trench is proximate at least one side of one of the first source region and the first drain region, the first isolation structure inducing only a portion of the first type of stress in the first channel region.
 57. The structure of claim 56, further comprising: a stressed layer disposed over the substrate, wherein at least a portion of the first channel region is disposed in the stressed layer, and the stressed layer comprises at least one of a group II, group III, group V, and group VI element.
 58. The structure of claim 56, further comprising: a first stress-inducing element that induces stress in the first channel region; and a second stress-inducing element that induces stress in the first channel region, wherein the portion of the stress induced by the first isolation structure is approximately zero and the first stress-inducing element is different from the second stress-inducing element.
 59. The structure of claim 58 wherein the first stress-inducing element comprises a first cap layer disposed over a surface of the first transistor.
 60. The structure of claim 58 wherein the first stress-inducing element comprises the first gate.
 61. The structure of claim 58 wherein the first stress-inducing element comprises at least one of the first source region and the first drain region.
 62. A method for forming a semiconductor structure, the method comprising: providing a substrate; forming a first transistor over a first region of the substrate by: defining a first source region and a first drain region in a first portion of the substrate, defining a first channel region between the first source region and the first drain region, the first channel region having a first type of stress, and forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material; and forming a first trench proximate at least one side of one of the first source region and the first drain region; and forming a first isolation structure in the first trench, the first isolation structure tailored to induce only a portion of the first type of stress in the first channel region.
 63. The method of claim 62 wherein at least a portion of the stress in the first channel region is induced by the first gate.
 64. The method of claim 62, further comprising: providing a first stress-inducing element; and providing a second stress-inducing element different from the first stress-inducing element, wherein the portion of the stress induced by the first isolation structure is approximately zero.
 65. The method of claim 64 wherein the first stress-inducing element comprises a first cap layer disposed over a surface of the first transistor.
 66. The method of claim 64 wherein the first stress-inducing element comprises the first gate.
 67. The method of claim 64 wherein the first stress-inducing element comprises at least one of the first source region and the first drain region.
 68. The structure of claim 56, further comprising: a dielectric layer disposed beneath the first channel region.
 69. The structure of claim 56 wherein at least one of the first source region and the first drain region comprises a metal-semiconductor alloy, and the stress in the first channel region is induced by the metal-semiconductor alloy.
 70. The structure of claim 56 wherein the first transistor is disposed in a chip, the structure further comprising: a package housing the chip, wherein the package induces stress in the first channel region.
 71. The structure of claim 58 wherein the first stress-inducing element comprises a metal-semiconductor alloy region disposed within at least one of the first source region and the first drain region.
 72. The method of claim 62, further comprising: forming a metal-semiconductor alloy over at least one of the first source region and the first drain region, the metal-semiconductor alloy tailored to induce the first type of stress in the first channel region.
 73. The method of claim 63 wherein forming the first gate comprises depositing an overlayer over the first gate and annealing the first gate.
 74. The method of claim 63 wherein forming the first gate comprises forming a polycrystalline semiconductor layer over the substrate and reacting the polycrystalline semiconductor layer with a metal such that the first gate consists essentially of an alloy of the metal and the semiconductor layer.
 75. The method of claim 62 wherein the first transistor is disposed in a chip, the method further comprising: attaching the chip to a package, wherein at least a portion of the stress in the first channel region is induced by the package.
 76. The method of claim 64 wherein the first stress-inducing element comprises a metal-semiconductor alloy formed over at least one of the first source region and the first drain region.
 77. A method for forming a semiconductor structure, the method comprising: providing a substrate comprising a stressed layer having a first type of stress; forming a masking layer over the substrate such that the masking layer exerts a second type of stress on the stressed layer; removing the masking layer over a first portion of the substrate; and etching a trench in the first portion of the substrate.
 78. The method of claim 77 wherein the first type of stress and the second type of stress are different.
 79. The method of claim 77 wherein the masking layer comprises silicon nitride.
 80. The method of claim 77, further comprising forming a pad oxide layer over the substrate prior to forming the masking layer.
 81. A structure comprising: a substrate; a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of strain, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and a first trench structure disposed in a trench, wherein the trench is proximate at least one side of one of the first source region and the first drain region, the first trench structure inducing only a portion of the first type of strain in the first channel region.
 82. The structure of claim 81, further comprising: a strained layer disposed over the substrate.
 83. The structure of claim 82 wherein the strained layer comprises at least one of silicon and germanium.
 84. The structure of claim 82 wherein at least a portion of the first channel region is disposed in the strained layer.
 85. The structure of claim 82, further comprising: a dielectric layer disposed over the substrate, wherein the strained layer is disposed over and in contact with the dielectric layer.
 86. The structure of claim 81 wherein the first type of strain is tensile.
 87. The structure of claim 81 wherein the first type of strain is compressive.
 88. The structure of claim 81 wherein the substrate comprises at least one of silicon and germanium.
 89. The structure of claim 81 wherein the substrate comprises at least one element other than silicon.
 90. The structure of claim 89 wherein the other element is germanium.
 91. The structure of claim 81, further comprising: a first cap layer disposed over a surface of the first transistor, wherein the strain in the first channel region is induced by the first cap layer.
 92. The structure of claim 91 wherein the first cap layer comprises silicon nitride.
 93. The structure of claim 81 wherein the strain in the first channel region is induced by at least one of the first source region and the first drain region.
 94. The structure of claim 93 wherein the at least one of the first source region and the first drain region comprises a second material having a larger lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
 95. The structure of claim 94 wherein the second material comprises a material selected from the group consisting of SiGe and Ge.
 96. The structure of claim 93 wherein the at least one of the first source region and the first drain region comprises a second material having a smaller lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
 97. The structure of claim 96 wherein the second material comprises a material selected from the group consisting of SiGe, Si, and SiC.
 98. The structure of claim 81 wherein the strain in the first channel region is induced by the first gate.
 99. The structure of claim 98 wherein the first gate comprises material selected from the group consisting of metal silicide, metal germanosilicide, and metal germanocide.
 100. The structure of claim 81, further comprising: a second transistor disposed over a second region of the substrate, the second transistor including: a second source region and a second drain region disposed in a second portion of the substrate, a second channel region disposed between the second source region and the second drain region, the second channel region having a second type of strain, and a second gate disposed above the second channel region and between the second source and second drain regions, the second gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and a second trench structure disposed in a trench, wherein the trench is proximate at least one side of one of the second source region and the second drain region, the second trench structure inducing only a portion of the second type of strain in the second channel region.
 101. The structure of claim 100 wherein the first and second types of strain are different.
 102. The structure of claim 81 wherein the portion of the strain induced by the first trench structure is approximately zero.
 103. The structure of claim 102, further comprising: a first strain-inducing element; and a first epitaxial strained layer, wherein the first channel region is disposed within a portion of the first epitaxial strained layer and the first strain-inducing element induces only a portion of the strain in the first channel region.
 104. The structure of claim 103 wherein the first strain-inducing element comprises a first cap layer disposed over a surface of the first transistor.
 105. The structure of claim 103 wherein the first strain-inducing element comprises the first gate.
 106. The structure of claim 103 wherein the first strain-inducing element comprises at least one of the first source region and the first drain region.
 107. A method for forming a semiconductor structure, the method comprising: providing a substrate; forming a first transistor over a first region of the substrate by: defining a first source region and a first drain region in a first portion of the substrate, defining a first channel region between the first source region and the first drain region, the first channel region having a first type of strain, and forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; forming a first trench proximate at least one side of one of the first source region and the first drain region; and forming a first trench structure in the first trench, the first trench structure tailored to induce only a portion of the first type of strain in the first channel region.
 108. The method of claim 107, further comprising: forming a second transistor over a second region of the substrate by: defining a second source region and a second drain region in a second portion of the substrate, defining a second channel region between the second source region and the second drain region, the second channel region having a second type of strain, and forming a second gate above the second channel region and between the second source and second drain regions, the second gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; forming a second trench proximate at least one side of one of the second source region and the second drain region; and forming a second trench structure in the second trench, the second trench structure tailored to induce only a portion of the second type of strain in the second channel region.
 109. The method of claim 108 wherein the first and second types of strain are different.
 110. The method of claim 107, further comprising: forming a first cap layer over a surface of the first transistor, the cap layer tailored to induce the first type of strain in the first channel region.
 111. The method of claim 107 wherein at least a portion of the strain in the first channel region is induced by at least one of the first source region and the first drain region.
 112. The method of claim 111 wherein the at least one of the first source region and the first drain region comprises a second material having a larger lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
 113. The method of claim 111 wherein the at least one of the first source region and the first drain region comprises a second material having a smaller lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
 114. The method of claim 107 wherein at least a portion of the strain in the first channel region is induced by the first gate.
 115. The method of claim 107 wherein the portion of the first type of strain the first trench structure is tailored to induce is approximately zero.
 116. The method of claim 115 wherein the first channel region is defined in a portion of a first epitaxial strained layer.
 117. The method of claim 115, further comprising: providing a first strain-inducing element.
 118. The method of claim 117 wherein the first strain-inducing element comprises a first cap layer disposed over a surface of the first transistor.
 119. The method of claim 117 wherein the first strain-inducing element comprises the first gate.
 120. The method of claim 117 wherein the first strain-inducing element comprises at least one of the first source region and the first drain region.
 121. A structure comprising: a substrate; a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of stress, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and a first trench structure disposed in a trench, wherein the trench is proximate at least one side of one of the first source region and the first drain region, the first trench structure inducing only a portion of the first type of stress in the first channel region.
 122. The structure of claim 121, further comprising: a stressed layer disposed over the substrate.
 123. The structure of claim 122 wherein the stressed layer comprises at least one of silicon and germanium.
 124. The structure of claim 122 wherein at least a portion of the first channel region is disposed in the stressed layer.
 125. The structure of claim 122, further comprising: a dielectric layer disposed over the substrate, wherein the stressed layer is disposed over and in contact with the dielectric layer.
 126. The structure of claim 121 wherein the first type of stress is tensile.
 127. The structure of claim 121 wherein the first type of stress is compressive.
 128. The structure of claim 121 wherein the substrate comprises at least one of silicon and germanium.
 129. The structure of claim 121 wherein the substrate comprises at least one element other than silicon.
 130. The structure of claim 129 wherein the other element is germanium.
 131. The structure of claim 121, further comprising: a first cap layer disposed over a surface of the first transistor, wherein the stress in the first channel region is induced by the first cap layer.
 132. The structure of claim 131 wherein the first cap layer comprises silicon nitride.
 133. The structure of claim 121 wherein the stress in the first channel region is induced by at least one of the first source region and the first drain region.
 134. The structure of claim 133 wherein the at least one of the first source region and the first drain region comprises a second material having a larger lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
 135. The structure of claim 134 wherein the second material comprises a material selected from the group consisting of SiGe and Ge.
 136. The structure of claim 133 wherein the at least one of the first source region and the first drain region comprises a second material having a smaller lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
 137. The structure of claim 136 wherein the second material comprises a material selected from the group consisting of SiGe, Si, and SiC.
 138. The structure of claim 121 wherein the stress in the first channel region is induced by the first gate.
 139. The structure of claim 138 wherein the first gate comprises material selected from the group consisting of metal silicide, metal germanosilicide, and metal germanocide.
 140. The structure of claim 121, further comprising: a second transistor disposed over a second region of the substrate, the second transistor including: a second source region and a second drain region disposed in a second portion of the substrate, a second channel region disposed between the second source region and the second drain region, the second channel region having a second type of stress, and a second gate disposed above the second channel region and between the second source and second drain regions, the second gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and a second trench structure disposed in a trench, wherein the trench is proximate at least one side of one of the second source region and the second drain region, the second trench structure inducing only a portion of the second type of stress in the second channel region.
 141. The structure of claim 140 wherein the first and second types of stress are different.
 142. The structure of claim 121 wherein the portion of the stress induced by the first trench structure is approximately zero.
 143. The structure of claim 142, further comprising: a first stress-inducing element; and a first epitaxial stressed layer, wherein the first channel region is disposed within a portion of the first epitaxial stressed layer and the first stress-inducing element induces only a portion of the stress in the first channel region.
 144. The structure of claim 143 wherein the first stress-inducing element comprises a first cap layer disposed over a surface of the first transistor.
 145. The structure of claim 143 wherein the first stress-inducing element comprises the first gate.
 146. The structure of claim 143 wherein the first stress-inducing element comprises at least one of the first source region and the first drain region.
 147. A method for forming a semiconductor structure, the method comprising: providing a substrate; forming a first transistor over a first region of the substrate by: defining a first source region and a first drain region in a first portion of the substrate, defining a first channel region between the first source region and the first drain region, the first channel region having a first type of stress, and forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; forming a first trench proximate at least one side of one of the first source region and the first drain region; and forming a first trench structure in the first trench, the first trench structure tailored to induce only a portion of the first type of stress in the first channel region.
 148. The method of claim 147, further comprising: forming a second transistor over a second region of the substrate by: defining a second source region and a second drain region in a second portion of the substrate, defining a second channel region between the second source region and the second drain region, the second channel region having a second type of stress, and forming a second gate above the second channel region and between the second source and second drain regions, the second gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; forming a second trench proximate at least one side of one of the second source region and the second drain region; and forming a second trench structure in the second trench, the second trench structure tailored to induce only a portion of the second type of stress in the second channel region.
 149. The method of claim 148 wherein the first and second types of stress are different.
 150. The method of claim 147, further comprising: forming a first cap layer over a surface of the first transistor, the cap layer tailored to induce the first type of stress in the first channel region.
 151. The method of claim 147 wherein at least a portion of the stress in the first channel region is induced by at least one of the first source region and the first drain region.
 152. The method of claim 151 wherein the at least one of the first source region and the first drain region comprises a second material having a larger lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
 153. The method of claim 151 wherein the at least one of the first source region and the first drain region comprises a second material having a smaller lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
 154. The method of claim 147 wherein at least a portion of the stress in the first channel region is induced by the first gate.
 155. The method of claim 147 wherein the portion of the first type of stress the first trench structure is tailored to induce is approximately zero.
 156. The method of claim 155 wherein the first channel region is defined in a portion of a first epitaxial stressed layer.
 157. The method of claim 155, further comprising: providing a first stress-inducing element.
 158. The method of claim 157 wherein the first stress-inducing element comprises a first cap layer disposed over a surface of the first transistor.
 159. The method of claim 157 wherein the first stress-inducing element comprises the first gate.
 160. The method of claim 157 wherein the first stress-inducing element comprises at least one of the first source region and the first drain region. 